Reprogrammable integrated circuits (ICs) provide a great deal of flexibility and control to circuit designers. For example, an in-system programmable (ISP) device can be programmed while installed in an electronic system (i.e., mounted on a circuit board with other components), thereby allowing modifications or upgrades to be performed on a completed product without replacing any hardware. In a complex programmable logic device (CPLD), this reprogrammability is typically provided by an EEPROM (electrically erasable programmable read-only memory) array.
FIG. 1 shows an electronic system 190 that includes a conventional CPLD 100. CPLD 100 comprises a configuration control circuit 110, an EEPROM array 120, and a configurable logic space 130 that includes a programmable interconnect matrix 131 and macrocells 132a-132d. Configuration control circuit 110 is coupled to receive an instruction INST and provide in response a configuration control signal CFG_CTRL that controls the loading of a set of configuration data CFG_DAT into EEPROM array 120. This in turn places interconnect matrix 131 and macrocells 132a-132d into a desired configuration.
The major benefit provided by EEPROM array 120 is the ability to change the functionality of CPLD 100 (and therefore electronic system 190) by reprogramming EEPROM array 120 with new configuration data. FIG. 2a shows a conventional process for this reconfiguration operation as applied to system 190 shown in FIG. 1. In step 210, power is provided to system 190, and in step 220, a set of configuration data (configuration data CFG_DAT shown in FIG. 1) is programmed into EEPROM array 120. Once the programmed data has been verified, system 190 can begin operating with CPLD 100 in a first configuration (configuration A), as indicated in step 230.
To reconfigure CPLD 100, the outputs of CPLD 100 are tri-stated, which halts operation of system 190, as shown in step 240. EEPROM 120 is then reprogrammed and verified with a new set of configuration data in step 250. System 190 is restarted in step 260, resuming operation with CPLD 1.00 in a new configuration (configuration B) in step 270. Thus, EEPROM 120 allows CPLD 100 to be reconfigured without making any hardware modifications. CPLD 100 therefore can be designated an in-system programmable (ISP) device.
This ISP capability of CPLD 100 provides substantial operational flexibility to electronic system 190. Unfortunately, the conventional reconfiguration process shown in FIG. 2a requires that operation of system 190 be halted (step 240) while EEPROM array 120 is reprogrammed with the new configuration data (step 250). This interruption of system operation is necessitated by the long programming time associated with EEPROM array 120. For a modern EEPROM array in a CPLD, the programming time is roughly equal to 10 ms multiplied by the number of row addresses in the EEPROM array, which can result in programming times of several seconds. The programming interval will only increase as the complexity of the interconnect array and the number of macrocells in the CPLD increase. The overall system downtime during reconfiguration also includes overhead associated with preparing for the EEPROM programming operation and also restarting system operation.
FIG. 2b shows a timing diagram for the initial configuration and subsequent reconfiguration operations described with respect to FIG. 2a, and shows traces for system power (Vdd), operation of system 190, and programming of EEPROM array 120. As shown in FIG. 2b, when system power is first applied at time T0, EEPROM programming commences. Once the programming of EEPROM array 120 is completed at time T1, system 190 can begin operating with CPLD 100 in a first configuration (configuration A). To place CPLD 100 in a different configuration, operation of system 190 is halted at time T2, and reprogramming of EEPROM 120 is performed. At time T3, this reprogramming is completed and system 190 can resume operation, this time with CPLD 100 in a second configuration (configuration B). As indicated in FIG. 2b, the time period between times T0 and T1 corresponds to the “CPLD Configuration at Power-Up” portion of the flow chart shown in FIG. 2a (steps 210 and 220). Similarly, the time period between times T1 and T2 corresponds to step 230, while the time period between times T2 and T3 corresponds to steps 240, 250, and 260 (“CPLD Reconfiguration”). Finally, the portion of the timing diagram after time T3 corresponds to step 270.
As noted previously, the downtime system 190 experienced during the reconfiguration operation from time T2 to time T3 is necessary to allow CPLD 100 to be reconfigured. In a conventional CPLD that follows the IEEE 1532 standard for ISP use, the only way to reconfigure the system is to apply an ISC_ENABLE instruction that halts the system (by tri-stating the CPLD outputs) to allow the new configuration data to be loaded into the EEPROM array. While this type of operational interruption may be acceptable in certain situations, in general it is much more desirable to minimize or eliminate any system downtime.
Accordingly, it is desirable to provide a system and method for reconfiguring a CPLD without interrupting system operation.
A desirable feature that can be included in CPLDs such as CPLD 100 is a “security feature” by means of which the configuration data set stored in EEPROM array 120 is secured from being either read or overwritten. Securing EEPROM array 120 from reading secures the configuration data set stored by the user from being read from the device, e.g., for purposes of copying the design. Securing EEPROM array 120 from writing prevents the accidental overwriting of the stored data, e.g., by inadvertently enabling configuration control circuit 110. Therefore, a security feature is a desirable addition for a CPLD in many applications.
Therefore, it is desirable to provide a system and method for reconfiguring a CPLD having a security feature without interrupting system operation.